A Discrete-Event Network Simulator
API
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ff-mac-common.h
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1/*
2 * Copyright (c) 2011 Centre Tecnologic de Telecomunicacions de Catalunya (CTTC)
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 *
6 * Author: Manuel Requena <manuel.requena@cttc.es>
7 */
8
9#ifndef FF_MAC_COMMON_H
10#define FF_MAC_COMMON_H
11
12#include <ns3/ptr.h>
13#include <ns3/simple-ref-count.h>
14
15#include <vector>
16
17/**
18 * Constants. See section 4.4
19 */
20#define MAX_SCHED_CFG_LIST 10
21#define MAX_LC_LIST 10
22
23#define MAX_RACH_LIST 30
24#define MAX_DL_INFO_LIST 30
25#define MAX_BUILD_DATA_LIST 30
26#define MAX_BUILD_RAR_LIST 10
27#define MAX_BUILD_BC_LIST 3
28#define MAX_UL_INFO_LIST 30
29#define MAX_DCI_LIST 30
30#define MAX_PHICH_LIST 30
31#define MAX_TB_LIST 2
32#define MAX_RLC_PDU_LIST 30
33#define MAX_NR_LCG 4
34#define MAX_MBSFN_CONFIG 5
35#define MAX_SI_MSG_LIST 32
36#define MAX_SI_MSG_SIZE 65535
37
38#define MAX_CQI_LIST 30
39#define MAX_UE_SELECTED_SB 6
40#define MAX_HL_SB 25
41#define MAX_SINR_RB_LIST 100
42#define MAX_SR_LIST 30
43#define MAX_MAC_CE_LIST 30
44
45namespace ns3
46{
47
48/// Result_e enumeration
54
55/// SetupRelease_e enumeration
61
62/// CeBitmap_e
64{
67 CR
68};
69
70/// NormalExtended_e enumeration
76
77/**
78 * \brief See section 4.3.1 dlDciListElement
79 * \struct DlDciListElement_s
80 */
82{
83 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
84 uint32_t m_rbBitmap{UINT8_MAX}; ///< RB bitmap
85 uint8_t m_rbShift{UINT8_MAX}; ///< RB shift
86 uint8_t m_resAlloc{UINT8_MAX}; ///< The type of resource allocation
87 std::vector<uint16_t> m_tbsSize; ///< The TBs size
88 std::vector<uint8_t> m_mcs; ///< MCS
89 std::vector<uint8_t> m_ndi; ///< New data indicator
90 std::vector<uint8_t> m_rv; ///< Redundancy version
91 uint8_t m_cceIndex{UINT8_MAX}; ///< Control Channel Element index
92 uint8_t m_aggrLevel{UINT8_MAX}; ///< The aggregation level
93 uint8_t m_precodingInfo{UINT8_MAX}; ///< precoding info
94
95 /// Format enumeration
108
109 uint8_t m_tpc{UINT8_MAX}; ///< Tx power control command
110 uint8_t m_harqProcess{UINT8_MAX}; ///< HARQ process
111 uint8_t m_dai{UINT8_MAX}; ///< DL assignment index
112
113 /// Vrb Format enum
120
121 bool m_tbSwap{false}; ///< swap?
122 bool m_spsRelease{false}; ///< release?
123 bool m_pdcchOrder{false}; ///< cch order?
124 uint8_t m_preambleIndex{UINT8_MAX}; ///< preamble index
125 uint8_t m_prachMaskIndex{UINT8_MAX}; ///< RACH mask index
126
127 /// Ngap enum
129 {
133 } m_nGap{NotValid_Ngap}; ///< the gap
134
135 uint8_t m_tbsIdx{UINT8_MAX}; ///< tbs index
136 uint8_t m_dlPowerOffset{UINT8_MAX}; ///< DL power offset
137 uint8_t m_pdcchPowerOffset{UINT8_MAX}; ///< CCH power offset
138};
139
140/**
141 * \brief See section 4.3.2 ulDciListElement
142 * \struct UlDciListElement_s
143 */
145{
146 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
147 uint8_t m_rbStart{UINT8_MAX}; ///< start
148 uint8_t m_rbLen{UINT8_MAX}; ///< length
149 uint16_t m_tbSize{UINT16_MAX}; ///< size
150 uint8_t m_mcs{UINT8_MAX}; ///< MCS
151 uint8_t m_ndi{UINT8_MAX}; ///< NDI
152 uint8_t m_cceIndex{UINT8_MAX}; ///< Control Channel Element index
153 uint8_t m_aggrLevel{UINT8_MAX}; ///< The aggregation level
154 uint8_t m_ueTxAntennaSelection{UINT8_MAX}; ///< UE antenna selection
155 bool m_hopping{false}; ///< hopping?
156 uint8_t m_n2Dmrs{UINT8_MAX}; ///< n2 DMRS
157 int8_t m_tpc{INT8_MIN}; ///< Tx power control command
158 bool m_cqiRequest{false}; ///< CQI request
159 uint8_t m_ulIndex{UINT8_MAX}; ///< UL index
160 uint8_t m_dai{UINT8_MAX}; ///< DL assignment index
161 uint8_t m_freqHopping{UINT8_MAX}; ///< freq hopping
162 int8_t m_pdcchPowerOffset{INT8_MIN}; ///< CCH power offset
163};
164
165/**
166 * \brief Base class for storing the values of vendor specific parameters
167 */
168struct VendorSpecificValue : public SimpleRefCount<VendorSpecificValue>
169{
170 virtual ~VendorSpecificValue();
171};
172
173/**
174 * \brief See section 4.3.3 vendorSpecificListElement
175 * \struct VendorSpecificListElement_s
176 */
178{
179 uint32_t m_type{UINT32_MAX}; ///< type
180 uint32_t m_length{UINT32_MAX}; ///< length
182};
183
184/**
185 * \brief See section 4.3.4 logicalChannelConfigListElement
186 * \struct LogicalChannelConfigListElement_s
187 */
189{
190 uint8_t m_logicalChannelIdentity{UINT8_MAX}; ///< logical channel identity
191 uint8_t m_logicalChannelGroup{UINT8_MAX}; ///< logical channel group
192
193 /// Direction enum
195 {
200 } m_direction{NotValid}; ///< the direction
201
202 /// QosBearerType enum
204 {
209 } m_qosBearerType{NotValid_QosBearerType}; ///< the QOS bearer type
210
211 uint8_t m_qci{UINT8_MAX}; ///< QCI
212 uint64_t m_eRabMaximulBitrateUl{UINT64_MAX}; ///< ERAB maximum bit rate UL
213 uint64_t m_eRabMaximulBitrateDl{UINT64_MAX}; ///< ERAB maximum bit rate DL
214 uint64_t m_eRabGuaranteedBitrateUl{UINT64_MAX}; ///< ERAB guaranteed bit rate UL
215 uint64_t m_eRabGuaranteedBitrateDl{UINT64_MAX}; ///< ERAB guaranteed bit rate DL
216};
217
218/**
219 * \brief See section 4.3.6 rachListElement
220 * \struct RachListElement_s
221 */
223{
224 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
225 uint16_t m_estimatedSize{UINT16_MAX}; ///< estimated size
226};
227
228/**
229 * \brief See section 4.3.7 phichListElement
230 * \struct PhichListElement_s
231 */
233{
234 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
235
236 /// Phich enum
238 {
242 } m_phich{NotValid}; ///< the phich
243};
244
245/**
246 * \brief See section 4.3.9 rlcPDU_ListElement
247 */
249{
250 uint8_t m_logicalChannelIdentity{UINT8_MAX}; ///< logical channel identity
251 uint16_t m_size{UINT16_MAX}; ///< size
252};
253
254/**
255 * \brief See section 4.3.8 buildDataListElement
256 * \struct BuildDataListElement_s
257 */
259{
260 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
261 struct DlDciListElement_s m_dci; ///< DCI
262 std::vector<CeBitmap_e> m_ceBitmap; ///< CE bitmap
263 std::vector<std::vector<struct RlcPduListElement_s>> m_rlcPduList; ///< RLC PDU list
264};
265
266/**
267 * \brief Substitutive structure for specifying BuildRarListElement_s::m_grant field
268 */
270{
271 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
272 uint8_t m_rbStart{UINT8_MAX}; ///< start
273 uint8_t m_rbLen{UINT8_MAX}; ///< length
274 uint16_t m_tbSize{UINT16_MAX}; ///< size
275 uint8_t m_mcs{UINT8_MAX}; ///< MCS
276 bool m_hopping{false}; ///< hopping?
277 int8_t m_tpc{INT8_MIN}; ///< Tx power control command
278 bool m_cqiRequest{false}; ///< CQI request?
279 bool m_ulDelay{false}; ///< UL delay?
280};
281
282/**
283 * \brief See section 4.3.10 buildRARListElement
284 */
286{
287 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
288 // uint32_t m_grant; // Substituted with type UlGrant_s
289 UlGrant_s m_grant; ///< grant
290 struct DlDciListElement_s m_dci; ///< DCI
291};
292
293/**
294 * \brief See section 4.3.11 buildBroadcastListElement
295 */
297{
298 /// Type enum
300 {
304 } m_type{NotValid}; ///< the type
305
306 uint8_t m_index{UINT8_MAX}; ///< index
307 struct DlDciListElement_s m_dci; ///< DCI
308};
309
310/**
311 * \brief See section 4.3.12 ulInfoListElement
312 */
314{
315 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
316 std::vector<uint16_t> m_ulReception; ///< UL reception
317
318 /// Reception status enum
320 {
324 } m_receptionStatus{NotValid}; ///< the status
325
326 uint8_t m_tpc{UINT8_MAX}; ///< Tx power control command
327};
328
329/**
330 * \brief See section 4.3.13 srListElement
331 */
333{
334 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
335};
336
337/**
338 * \brief See section 4.3.15 macCEValue
339 */
341{
342 uint8_t m_phr{UINT8_MAX}; ///< phr
343 uint8_t m_crnti{UINT8_MAX}; ///< NRTI
344 std::vector<uint8_t> m_bufferStatus; ///< buffer status
345};
346
347/**
348 * \brief See section 4.3.14 macCEListElement
349 */
351{
352 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
353
354 /// MAC CE type enum
356 {
361 } m_macCeType{NotValid}; ///< MAC CE type
362 struct MacCeValue_u m_macCeValue; ///< MAC CE value
363};
364
365/**
366 * \brief See section 4.3.16 drxConfig
367 */
369{
370 uint8_t m_onDurationTimer{UINT8_MAX}; ///< on duration timer
371 uint16_t m_drxInactivityTimer{UINT16_MAX}; ///< inactivity timer
372 uint16_t m_drxRetransmissionTimer{UINT16_MAX}; ///< retransmission timer
373 uint16_t m_longDrxCycle{UINT16_MAX}; ///< long DRX cycle
374 uint16_t m_longDrxCycleStartOffset{UINT16_MAX}; ///< long DRX cycle start offset
375 uint16_t m_shortDrxCycle{UINT16_MAX}; ///< short DRX cycle
376 uint8_t m_drxShortCycleTimer{UINT8_MAX}; ///< short DRX cycle timer
377};
378
379/**
380 * \brief See section 4.3.17 spsConfig
381 */
383{
384 uint16_t m_semiPersistSchedIntervalUl{UINT16_MAX}; ///< UL semi persist schedule interval
385 uint16_t m_semiPersistSchedIntervalDl{UINT16_MAX}; ///< DL semi persist schedule interval
386 uint8_t m_numberOfConfSpsProcesses{UINT8_MAX}; ///< number of conf SPS process
387 uint8_t m_n1PucchAnPersistentListSize{UINT8_MAX}; ///< N1pu CCH persistent list size
388 std::vector<uint16_t> m_n1PucchAnPersistentList; ///< N1pu CCH persistent list
389 uint8_t m_implicitReleaseAfter{UINT8_MAX}; ///< implicit release after
390};
391
392/**
393 * \brief See section 4.3.18 srConfig
394 */
396{
397 /// Actions
399 {
400 setup
401 };
402
404 uint8_t m_schedInterval{UINT8_MAX}; ///< sched interval
405 uint8_t m_dsrTransMax{UINT8_MAX}; ///< trans max
406};
407
408/**
409 * \brief See section 4.3.19 cqiConfig
410 */
412{
413 /// Actions
415 {
416 setup
417 };
418
419 SetupRelease_e m_action; ///< CQI action
420 uint16_t m_cqiSchedInterval{UINT16_MAX}; ///< CQI schedule interval
421 uint8_t m_riSchedInterval{UINT8_MAX}; ///< RI schedule interval
422};
423
424/**
425 * \brief See section 4.3.20 ueCapabilities
426 */
428{
429 bool m_halfDuplex{false}; ///< half duplex
430 bool m_intraSfHopping{false}; ///< intra SF hopping
431 bool m_type2Sb1{false}; ///< type 2Sb1
432 uint8_t m_ueCategory{UINT8_MAX}; ///< UE category
433 bool m_resAllocType1{false}; ///< alloc type 1
434};
435
436/**
437 * \brief See section 4.3.22 siMessageListElement
438 */
440{
441 uint16_t m_periodicity{UINT16_MAX}; ///< periodicity
442 uint16_t m_length{UINT16_MAX}; ///< length
443};
444
445/**
446 * \brief See section 4.3.21 siConfiguration
447 */
449{
450 uint16_t m_sfn{UINT16_MAX}; ///< sfn
451 uint16_t m_sib1Length{UINT16_MAX}; ///< sib1 length
452 uint8_t m_siWindowLength{UINT8_MAX}; ///< window length
453 std::vector<struct SiMessageListElement_s> m_siMessageList; ///< message list
454};
455
456/**
457 * \brief See section 4.3.23 dlInfoListElement
458 */
460{
461 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
462 uint8_t m_harqProcessId{UINT8_MAX}; ///< HARQ process ID
463
464 /// HARQ status enum
471
472 std::vector<HarqStatus_e> m_harqStatus; ///< HARQ status
473};
474
475/**
476 * \brief See section 4.3.28 bwPart
477 */
479{
480 uint8_t m_bwPartIndex{UINT8_MAX}; ///< bw part index
481 uint8_t m_sb{UINT8_MAX}; ///< sb
482 uint8_t m_cqi{UINT8_MAX}; ///< CQI
483};
484
485/**
486 * \brief See section 4.3.27 higherLayerSelected
487 */
489{
490 uint8_t m_sbPmi{UINT8_MAX}; ///< sb PMI
491 std::vector<uint8_t> m_sbCqi; ///< sb CQI
492};
493
494/**
495 * \brief See section 4.3.26 ueSelected
496 */
498{
499 std::vector<uint8_t> m_sbList; ///< sb list
500 uint8_t m_sbPmi{UINT8_MAX}; ///< sb PMI
501 std::vector<uint8_t> m_sbCqi; ///< sb CQI
502};
503
504/**
505 * \brief See section 4.3.25 sbMeasResult
506 */
508{
509 struct UeSelected_s m_ueSelected; ///< UE selected
510 std::vector<struct HigherLayerSelected_s> m_higherLayerSelected; ///< higher layer selected
511 struct BwPart_s m_bwPart; ///< bw part
512};
513
514/**
515 * \brief See section 4.3.24 cqiListElement
516 */
518{
519 uint16_t m_rnti{UINT16_MAX}; ///< RNTI
520 uint8_t m_ri{UINT8_MAX}; ///< RI
521
522 /// CqiType_e enumeration
524 {
535 } m_cqiType{NotValid}; ///< CQI type
536
537 std::vector<uint8_t> m_wbCqi; ///< wb CQI
538 uint8_t m_wbPmi{UINT8_MAX}; ///< wb PMI
539
540 struct SbMeasResult_s m_sbMeasResult; ///< sb measure result
541};
542
543/**
544 * \brief See section 4.3.29 ulCQI
545 */
547{
548 std::vector<uint16_t> m_sinr; ///< SINR
549
550 /// Type_e enumeration
560};
561
562/**
563 * \brief See section 4.3.30 pagingInfoListElement
564 */
566{
567 uint8_t m_pagingIndex{UINT8_MAX}; ///< paging index
568 uint16_t m_pagingMessageSize{UINT16_MAX}; ///< paging message size
569 uint8_t m_pagingSubframe{UINT8_MAX}; ///< paging subframe
570};
571
572} // namespace ns3
573
574#endif /* FF_MAC_COMMON_H */
Smart pointer class similar to boost::intrusive_ptr.
A template-based reference counting class.
Every class exported by the ns3 library is enclosed in the ns3 namespace.
SetupRelease_e
SetupRelease_e enumeration.
@ release
Result_e
Result_e enumeration.
@ FAILURE
@ SUCCESS
CeBitmap_e
CeBitmap_e.
NormalExtended_e
NormalExtended_e enumeration.
@ extended
See section 4.3.11 buildBroadcastListElement.
enum ns3::BuildBroadcastListElement_s::Type_e NotValid
the type
struct DlDciListElement_s m_dci
DCI.
See section 4.3.8 buildDataListElement.
std::vector< std::vector< struct RlcPduListElement_s > > m_rlcPduList
RLC PDU list.
std::vector< CeBitmap_e > m_ceBitmap
CE bitmap.
struct DlDciListElement_s m_dci
DCI.
See section 4.3.10 buildRARListElement.
struct DlDciListElement_s m_dci
DCI.
See section 4.3.28 bwPart.
uint8_t m_cqi
CQI.
uint8_t m_bwPartIndex
bw part index
See section 4.3.19 cqiConfig.
uint8_t m_riSchedInterval
RI schedule interval.
SetupRelease_e m_action
CQI action.
uint16_t m_cqiSchedInterval
CQI schedule interval.
See section 4.3.24 cqiListElement.
std::vector< uint8_t > m_wbCqi
wb CQI
struct SbMeasResult_s m_sbMeasResult
sb measure result
CqiType_e
CqiType_e enumeration.
enum ns3::CqiListElement_s::CqiType_e NotValid
CQI type.
See section 4.3.1 dlDciListElement.
uint8_t m_prachMaskIndex
RACH mask index.
uint8_t m_cceIndex
Control Channel Element index.
std::vector< uint8_t > m_ndi
New data indicator.
enum ns3::DlDciListElement_s::VrbFormat_e NotValid_VRB_Format
the format
uint8_t m_dai
DL assignment index.
uint8_t m_precodingInfo
precoding info
uint8_t m_harqProcess
HARQ process.
uint32_t m_rbBitmap
RB bitmap.
bool m_pdcchOrder
cch order?
enum ns3::DlDciListElement_s::Ngap_e NotValid_Ngap
the gap
VrbFormat_e
Vrb Format enum.
enum ns3::DlDciListElement_s::Format_e NotValid_Dci_Format
the format
Format_e
Format enumeration.
uint8_t m_preambleIndex
preamble index
uint8_t m_dlPowerOffset
DL power offset.
uint8_t m_pdcchPowerOffset
CCH power offset.
std::vector< uint8_t > m_mcs
MCS.
uint8_t m_rbShift
RB shift.
uint8_t m_resAlloc
The type of resource allocation.
uint8_t m_aggrLevel
The aggregation level.
std::vector< uint16_t > m_tbsSize
The TBs size.
std::vector< uint8_t > m_rv
Redundancy version.
uint8_t m_tpc
Tx power control command.
uint8_t m_tbsIdx
tbs index
See section 4.3.23 dlInfoListElement.
uint8_t m_harqProcessId
HARQ process ID.
HarqStatus_e
HARQ status enum.
std::vector< HarqStatus_e > m_harqStatus
HARQ status.
See section 4.3.16 drxConfig.
uint16_t m_longDrxCycleStartOffset
long DRX cycle start offset
uint16_t m_drxInactivityTimer
inactivity timer
uint16_t m_longDrxCycle
long DRX cycle
uint8_t m_drxShortCycleTimer
short DRX cycle timer
uint16_t m_drxRetransmissionTimer
retransmission timer
uint16_t m_shortDrxCycle
short DRX cycle
uint8_t m_onDurationTimer
on duration timer
See section 4.3.27 higherLayerSelected.
std::vector< uint8_t > m_sbCqi
sb CQI
See section 4.3.4 logicalChannelConfigListElement.
enum ns3::LogicalChannelConfigListElement_s::QosBearerType_e NotValid_QosBearerType
the QOS bearer type
uint64_t m_eRabMaximulBitrateUl
ERAB maximum bit rate UL.
uint64_t m_eRabGuaranteedBitrateDl
ERAB guaranteed bit rate DL.
uint8_t m_logicalChannelGroup
logical channel group
uint64_t m_eRabGuaranteedBitrateUl
ERAB guaranteed bit rate UL.
enum ns3::LogicalChannelConfigListElement_s::Direction_e NotValid
the direction
uint8_t m_logicalChannelIdentity
logical channel identity
uint64_t m_eRabMaximulBitrateDl
ERAB maximum bit rate DL.
See section 4.3.14 macCEListElement.
struct MacCeValue_u m_macCeValue
MAC CE value.
MacCeType_e
MAC CE type enum.
enum ns3::MacCeListElement_s::MacCeType_e NotValid
MAC CE type.
See section 4.3.15 macCEValue.
std::vector< uint8_t > m_bufferStatus
buffer status
uint8_t m_crnti
NRTI.
See section 4.3.30 pagingInfoListElement.
uint8_t m_pagingSubframe
paging subframe
uint8_t m_pagingIndex
paging index
uint16_t m_pagingMessageSize
paging message size
See section 4.3.7 phichListElement.
enum ns3::PhichListElement_s::Phich_e NotValid
the phich
See section 4.3.6 rachListElement.
uint16_t m_estimatedSize
estimated size
See section 4.3.9 rlcPDU_ListElement.
uint8_t m_logicalChannelIdentity
logical channel identity
See section 4.3.25 sbMeasResult.
std::vector< struct HigherLayerSelected_s > m_higherLayerSelected
higher layer selected
struct BwPart_s m_bwPart
bw part
struct UeSelected_s m_ueSelected
UE selected.
See section 4.3.21 siConfiguration.
std::vector< struct SiMessageListElement_s > m_siMessageList
message list
uint16_t m_sib1Length
sib1 length
uint8_t m_siWindowLength
window length
See section 4.3.22 siMessageListElement.
uint16_t m_periodicity
periodicity
See section 4.3.17 spsConfig.
uint8_t m_implicitReleaseAfter
implicit release after
std::vector< uint16_t > m_n1PucchAnPersistentList
N1pu CCH persistent list.
uint8_t m_n1PucchAnPersistentListSize
N1pu CCH persistent list size.
uint16_t m_semiPersistSchedIntervalUl
UL semi persist schedule interval.
uint16_t m_semiPersistSchedIntervalDl
DL semi persist schedule interval.
uint8_t m_numberOfConfSpsProcesses
number of conf SPS process
See section 4.3.18 srConfig.
uint8_t m_dsrTransMax
trans max
SetupRelease_e m_action
action
uint8_t m_schedInterval
sched interval
See section 4.3.13 srListElement.
See section 4.3.20 ueCapabilities.
bool m_type2Sb1
type 2Sb1
bool m_intraSfHopping
intra SF hopping
bool m_resAllocType1
alloc type 1
bool m_halfDuplex
half duplex
uint8_t m_ueCategory
UE category.
See section 4.3.26 ueSelected.
std::vector< uint8_t > m_sbList
sb list
uint8_t m_sbPmi
sb PMI
std::vector< uint8_t > m_sbCqi
sb CQI
See section 4.3.29 ulCQI.
enum ns3::UlCqi_s::Type_e NotValid
type
std::vector< uint16_t > m_sinr
SINR.
Type_e
Type_e enumeration.
See section 4.3.2 ulDciListElement.
int8_t m_pdcchPowerOffset
CCH power offset.
int8_t m_tpc
Tx power control command.
uint8_t m_dai
DL assignment index.
uint8_t m_cceIndex
Control Channel Element index.
uint8_t m_ulIndex
UL index.
uint8_t m_ueTxAntennaSelection
UE antenna selection.
bool m_cqiRequest
CQI request.
uint8_t m_freqHopping
freq hopping
uint8_t m_aggrLevel
The aggregation level.
Substitutive structure for specifying BuildRarListElement_s::m_grant field.
bool m_ulDelay
UL delay?
int8_t m_tpc
Tx power control command.
bool m_cqiRequest
CQI request?
bool m_hopping
hopping?
uint16_t m_tbSize
size
uint8_t m_rbLen
length
uint8_t m_mcs
MCS.
uint8_t m_rbStart
start
uint16_t m_rnti
RNTI.
See section 4.3.12 ulInfoListElement.
ReceptionStatus_e
Reception status enum.
uint8_t m_tpc
Tx power control command.
enum ns3::UlInfoListElement_s::ReceptionStatus_e NotValid
the status
std::vector< uint16_t > m_ulReception
UL reception.
See section 4.3.3 vendorSpecificListElement.
Ptr< VendorSpecificValue > m_value
value
Base class for storing the values of vendor specific parameters.